I. Parallel Processing inside RISC Processors

Parallel Implementation of Neural Associative Memories on Risc Processors

Optimum Complexity FFT Algorithms for RISC Processors

Modern RISC processors provide a special instruction { the fused multiplyadd (FMA) instruction a b c { to perform both a multiplication and an addition operation at the same time. In this paper newly developed radix-2, radix-4, and split-radix FFT algorithms that optimally take advantage of this powerful instruction are presented. All oating-point operations of these algorithms are executed as ...

Portable Execution Time Analysis for RISC Processors

The knowledge of a task’s worst case execution time (WCET) is required for scheduling real-time tasks. Existing execution time analyzers are machine dependent and this is a serious problem as architectures evolve rapidly. In this paper, we present a tool for portable execution time analysis for RISC processors. This tool generates an execution time analyzer for any RISC processor. The analyzer ...

Retargetable Timing Analyzer for Risc Processors

The objective of this paper is to present a software tool, called retargetable timing analyzer generator (RTAG), which takes as input an architecture description and automatically generates a pipeline an-alyzer to resolve the portability problem. We explain our methodology for worst case execution time analysis and describe how it is reeected in the timing analyzer generator. The generator take...

Optimisation for Vector and Risc Processors

Single node performance is a key issue in the optimisation of codes for massively parallel processors, especially for applications like ocean and atmospheric modelling where high parallel efficiency is easily obtained from the natural data locality. In this paper we demonstrate how specific optimisations to suit a particular target processor architecture can give significant performance benefit...